1. Field of the Invention
This invention relates to an insulated gate bipolar transistor which can be used as an element of an electric switch for electric power.
2. Description of the Related Arts
There have been many reports recently related to an insulated gate bipolar transistor used as an element of an electric switch for electric power.
This kind of element usually has a P-N-P-N configuration similar to that of a usual power MOSFET, but this insulated gate bipolar transistor enables a high withstand voltage and a low ON resistance to be obtained simultaneously, which has been heretofore considered impossible in a usual power MOSFET, by reducing the ON resistance caused by a modulation of a conductivity of a drain layer having a high resistance layer by providing a semiconductor layer, having an opposite type of conductivity to a source layer, in a drain region.
This kind of insulated gate bipolar transistor has a P-N-P-N four layered construction between a drain electrode and a source electrode. Although it is similar to a thyristor, it does not work as a thyristor because the source electrode thereof causes a short circuit between a P-type base layer and N.sup.+ -type source layer, and the semiconductor element is always turned OFF by setting the voltage between a gate electrode and a source electrode to zero.
Nevertheless, another problem arises with this kind of insulated gate bipolar transistor. Namely, when a current density which flows in the element is increased, a voltage drop caused by a transverse resistance existing under a source layer is also increased, and therefore, this element is forced to work as a thyristor because the junction surface between the P-type base layer and N.sup.+ -type source layer is forward biased, and accordingly, a latch up phenomenon occurs in which, even when a bias between a gate and a source is set to zero, the current of the semiconductor element is not turned OFF.
To overcome the above problem, a method in which the latch up phenomenon can be prevented even in a region in which a large amount of current is used, by minimizing the transverse voltage drop caused by lowering the resistance of the base layer just below the source layer, was proposed in, for example, Japanese Unexamined Patent Publication No. 60-196974.
Nevertheless, if the operating temperature is higher than 125.degree. C., even if only a slight transverse voltage drop in the base layer existing just below the source layer occurs, the junction surface between the P-type base layer and N.sup.+ -type source layer will be forward biased and the above latch up phenomenon will occur, and therefore, this method does not solve the above problem.
Further, even when operating at room temperature, if there is a flow of a large amount of current greater than the current flowing in a region wherein a latch up phenomenon has never occurred, the latch up phenomenon will ultimately occur and, consequently, the basic cause of this latch up phenomenon can not be removed.